1. Field of the Invention
This invention relates to a digital video tape recorder (DVTR) wherein discrete cosine transformation (hereinafter referred to as DCT) and variable length coding are employed for compressing the data to be recorded.
2. Description of the Related Art
Professional or broadcasting digital video tape recorders embodying the D1 format, the D2 format and the D3 format have been placed on the market. In addition, various formats have been proposed for consumer-type digital video tape recorders in order to promote the more widespread use of digital video tape recorders.
Referring now to FIG. 2 which shows the general construction of a video signal processing system of a digital video tape recorder employing DCT and variable length coding for data compression, it will be seen that the video input signals in the form of analog component video signals (Y, R-Y, B-Y) are supplied to an analog to digital (A/D) converter 1 for sampling therein, for example, at the ratio of 4:1:1 (with the Y signal being sampled at the rate of 13.5 MHz, and the R-Y signal and the B-Y signal being each sampled at the rate of 3.375 MHz). Alternatively, the analog component video signals (Y, R-Y, B-Y) may be sampled at the ratio of 4:2:0 (with the Y signal being sampled at the rate of 13.5 MHz, and the R-Y signal and the B-Y signal being sampled line-sequentially at the rate of 6.75 MHz). The A/D converter 1 converts the sampled video signals into digital data supplied to a block segmentation circuit 2 in which the digital data are formed into data blocks each including 8 samples in each line in the horizontal direction and 8 lines in the vertical direction (hereinafter referred to as an 8.times.8 data unit). The resultant data is shuffled and Y/C-multiplexed. Each of the 8.times.8 units is then discrete cosine transformed by a DCT circuit 3 to convert the data therein from the time domain into the frequency domain, so that each DCT converted block (hereinafter referred to as a DCT block) includes a DC component and one or more AC components. The discrete-cosine-transformed data is then re-quantized by an encoder 4 and variable-length encoded therein for data compression by a technique such as two-dimensional Huffman coding.
In the above-described system, the step width used in the re-quantization process is selected separately for each successive group of thirty DCT blocks, each group also being referred to herein as a buffering unit, so that when the data is re-quantized the amount thereof will not exceed a certain level, that is, each buffering unit has a fixed length. The thirty DCT blocks of each buffering unit may, for example, consist of twenty DCT blocks of the Y signal and ten DCT blocks of the C signal, with each buffering unit being formed into, for example, five macroblocks (FIG. 3(c)) each including six DCT blocks of data arranged successively as two luminance blocks Y, followed by a color component block C, followed in turn by a further two luminance blocks Y and finally followed by a color component block C. A framing circuit 5 serves to vertically align a plurality of buffering units as described above into a larger unit which is combined with an error correction code (ECC) by a parity generator 6. The data as thus constituted is then converted by means of a channel encoder 7 into serial form for recording. In the course of such recording, the data of one frame is divided among ten tracks, as shown in FIG. 3(a).
When the data in serial form is reproduced, it is detected and converted to parallel form by means of a channel decoder 8 and then error-corrected by an ECC circuit 9. The error-corrected data is then separated into the variable-length code words of each block by a de-framing circuit 10 and subsequently decoded and de-quantized by a decoder 11. The resultant data is then inversely discrete cosine transformed by an inverse DCT circuit (IDCT) 12 to yield 8.times.8 unit blocks of time domain data.
The data blocks as thus reproduced are de-shuffled, Y/C demultiplexed and data-interpolated by a block desegmentation circuit 13 to recover the digital component video signal. Finally, the digital video signal is converted by a D/A converter 14 into a reproduction of the original analog component video signal to be output by the reproducing system of FIG. 2.
The digital video tape recorder records the video data compressed by the video signal processing system described above along with compressed audio data, controlling digital subcodes, an ATF pilot signal for tracking control, ECC parities, preambles and postambles for the extraction of clocks and so forth in a predetermined track format on a magnetic tape. The signals described above for one frame are recorded segmentally or divisionally in a plurality of oblique tracks on the magnetic tape. For example, in the case of video signals according to the NTSC system, the compressed video data for each frame and the other associated data are recorded in ten oblique tracks on the magnetic tape.
The digital video tape recorder described above has the following numbered characteristics:
(1) Sampling frequency or rate ratio=4:1:1 or 4:2:0. PA1 (2) Effective Data: horizontal 720 dots.times.vertical 480 dots for the Y signal and horizontal 360 dots.times.vertical 480 dots for the C signal. Accordingly, 720.times.480+360.times.480=518,400 dots for each frame. PA1 (3) DCT in units of 8.times.8 data. PA1 (4) Variable length coded so that thirty DCT blocks may have a fixed length. PA1 (5) Segment recording of one frame divided among 10 tracks. Accordingly, 518,400.div.10.div.30.div.(8.times.8)=27 fixed length buffering units in each track, as on FIG. 3(a).
Signal processing clocks in the digital video tape recorder are selected in the following manner:
(a) The analog to digital converter 1 and the digital to analog converter 14 each operate with clock signals of 13.5 MHz and one half and one quarter of 13.5 MHz.
(b) The signal processing clock signal SCK of the recording and reproducing section constituted by the parity generation circuit 6, the channel encoder 7, the channel decoder 8 and the ECC circuit 9 is defined from a tape pattern and the speed of rotation of a head drum and includes a basic clock signal of 40 MHz or so and clock signals of one half and one quarter of 40 MHz.
(c) The signal processing clock signal TCK of the data compression section constituted by the block segmenting circuit 2, the DCT circuit 3, the encoding circuit 4 and the framing circuit 5, and of the data decompression section constituted by the deframing circuit 10, the decoding circuit 11, the IDCT circuit 12 and the block desegmenting circuit 13 is 518,400 (CLK) per frame. Since the NTSC field rate is actually 59.94 Hz, the frequency of the signal processing clock signal TCK is .apprxeq.15.54 MHz.
With the conventional digital video tape recorder, 64 clocks are allocated to each DCT block or unit, as shown in FIG. 3(e). Therefore, another signal line or channel is required for the transmission of information incidental to the principal data, such as motion information of the DCT blocks, activity information representative of the amount of high frequency components in a DCT block, data interpolation information and the like.
Further, in the event of fluctuations in the duration, timing, data amount and so forth of a video signal of one track actually reproduced in one track (TRK) period (FIG. 3(a)) of the video signal processing system described with reference to FIG. 2, for example, as in the case when variable speed reproduction is performed, then it is difficult to adapt operation of the signal processing system to the actual reproduced data.